Semiconductor Engineering

Low-Power SoC Design

Over the last decade, power has become the primary design constraint for all SoC designs. While power reduction started in mobile market segments due to the battery considerations, it quickly has ...
EDN

Methodology improves SoC power grids

SOC design comes with its own set of complications and challenges. One of the biggest challenges that arise is inherent limitation of particular technology node. As technologies are scaling down, it ...
EDN

Structural netlist efficiently verifies analog IP

One of the major issues faced in the verification of analog or AMS IP in the SOC environment is the behavioral model’s limitations. Since behavioral models are not perfectly able to replicate analog ...
Electronic Design

Manage ASIC, SoC Design Risk with Leading-Edge Verification Services

Value in design prototyping using FPGAs. Validating the design with firmware. How the process works. Identifying companies with the right experience and expertise in FPGA and design prototyping ...
Embedded

Using multi-bit flip-flop custom cells to achieve better SoC design efficiency

System-on-chip (SoC) designs are becoming more and more complex, by whatever means you measure it: power domains, gate count, packing densities, heat dissipation capacities, etc. At such high packing ...
Electronic Design

DFT Strategies for SOC Designs

Many IC designers finally have embraced design for testability (DFT) in the form of scan insertion for digital circuit designs because of the significant time-to-production advantages these techniques ...