EDN

Design clock controllers for hierarchical test

Hierarchical test methodologies are being broadly adopted for large designs. They provide roughly an order of magnitude better ATPG (automatic test program generation) run time, reduce workstation ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
Electronic Design

What’s The Difference Between Scan ATPG And IJTAG Pattern Retargeting?

Both scan automated test pattern generation (ATPG) patterns and IJTAG patterns 1,2,3 are created for a piece of logic that is part of a much larger design. For both, the patterns are independent from ...
Electronic Design

Clock Generators Bring Stability to Timing-Circuit Designs

Clock speed is equivalent to data movement in applications that receive and process hundreds of megabytes of data each second. Applications involved in moving enormous volumes of data include cellular ...
EDN

Sequential clock gating maximizes power savings at IP level

Power Management is one of the major chip design challenges amongst all the dimensions of the design cycle. It poses problems for packaging, portability, & reliability (PPR), e.g.,“high system cost of ...