EDN

Flip-Flop Using CMOS NAND Gates

Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...
EDN

Intel crafts transistor with 20-nm gate length

KYOTO, Japan — Intel Corp. researchers have provided a peek at a transistor with a gate length measuring just 20 nanometers, which Intel expects to put into production in 2007 when its microprocessors ...
ExtremeTech

Researchers create CMOS-compatible, 30nm programmable graphene transistor

Electronic engineers at Japan's GNC and AIST research centers have successfully created graphene transistors that are constructed and operated in a way that redefines 50 years of transistor ...
Business Wire

Search For The Next: UK Collaboration Unveils Bizen® a Transistor Wafer Process Technology Promising to Slash Lead Times, Wafer Area and Process Layers While Increasing Speed ...

NOTTINGHAM, England--(BUSINESS WIRE)--A UK collaboration between Nottingham-based start-up, Search For The Next (SFN) and Glenrothes-based Semefab may be set to disrupt the semiconductor industry by ...
Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...