EDN

Hybrid-gate-array technology promises shorter cycle time and lower NRE and unit costs

Targeting FPGA-to-ASIC conversions and first-time ASIC designs, a 0.18-micron, hybrid-process gate array from AMI Semiconductor hits a triple play of cutting cycle time, slashing up-front NRE costs, ...
Electronic Design

ASIC-Like FPGA Methodology Saves Up To $9,925,000 In NRE Costs

Not all companies have $10 million in their back pockets for the non-recurring expenses (NRE) today's ASIC design starts require. Fortunately, that kind of cash isn't necessary anymore, thanks to ...
EDN

ASIC firms travel many roads to cut costs

SAN JOSE, Calif. — Things could hardly be worse for vendors of custom ASICs. The cost of cell-based designs and the time it takes to complete them continue to rise, even as customers scramble for ways ...
Design-Reuse

ON Semiconductor Delivers Structured ASIC Technology for Military and Aerospace SoCs and FPGA-to-ASIC Conversions

PHOENIX -- March 18, 2008 -- ON Semiconductor, a global leader in power management solutions, has announced that XPressArray-II (XPA-II), a leading structured ASIC technology formerly offered by AMI ...