Morning Overview on MSN

MIT’s chip stacking leap could slash energy use for hungry AI chips

Artificial intelligence is colliding with a hard physical limit: the energy it takes to move data on and off chips. Training ...
TweakTown

Intel to bring 3D-Stacked Cache to its CPUs but it will be different from AMD's 3D V-Cache

At Intel's big Innovation 2023 event, CEO Pat Gelsinger confirmed that the company would adopt a 3D Cache approach for CPUs in the future - though it won't be a part of the upcoming Meteor Lake ...
IEEE Spectrum on MSN

The ultimate 3D integration would cook future GPUs

D stacking doubles the operating temperature inside the GPU, rendering it inoperable. But the team, led by Imec’s James Myers ...
Nasdaq

Soitec and PSMC collaborate on ultra-thin TLT technology for nm-scale 3D stacking

Bernin (France), June 3, 2025 – Soitec (Euronext – Tech Leaders), a world leader in the design and production of innovative semiconductor materials, today announced a strategic collaboration with ...
Digi Times

Samsung reportedly investing in R&D for 3D stacking GAA technology

After memory products like NAND Flash and DRAM, it's reported that Samsung Electronics will conduct R&D for a "3D stacking" technology that can vertically stack system semiconductor transistors.
TweakTown

Huawei to use HBM in smartphones with 3D stacking tech: will boost efficiency, AI performance

TL;DR: Huawei is set to lead Apple by integrating high-performance HBM DRAM with 3D stacking technology in smartphones, boosting AI efficiency and bandwidth while reducing chip size. Apple plans to ...
Semiconductor Engineering

Thermal Analysis Of 3D Stacking And BEOL Technologies With Functional Partitioning Of Many-Core RISC-V SoC

Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization ...
Digi Times

3D chip stacking tech competition intensifying

TSMC has recently announced SoIC-P, microbump versions of its System on Integrated Chips (SoIC) solutions providing a cost-effective way for 3D chip stacking. TSMC said SoIC-P complements its existing ...
Electronic Design

True-3D Chip-Layout Editor Facilitates Stacking Of Disparate Wafers

Say you wanted to create a chip in which a processor fabricated in 32-nm process rules would be combined with memory done on a 65-nm process and analog blocks fabricated at 180 nm. This leads you to ...
EurekAlert!

Thermal impact of 3D stacking photonic and electronic chips

Hybrid, 3D integrated optical transceiver. (A,B) The test setup: the photonic chip (PIC) is placed on a circuit board (green), and the electronic chip (EIC) is bonded on top of the photonic chip. (C) ...
Semiconductor Engineering

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher ...